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 DM74LS393 Dual 4-Bit Binary Counter
August 1986 Revised March 2000
DM74LS393 Dual 4-Bit Binary Counter
General Description
Each of these monolithic circuits contains eight masterslave flip-flops and additional gating to implement two individual four-bit counters in a single package. The DM74LS393 comprises two independent four-bit binary counters each having a clear and a clock input. N-bit binary counters can be implemented with each package providing the capability of divide-by-256. The DM74LS393 has parallel outputs from each counter stage so that any submultiple of the input count frequency is available for system-timing signals.
Features
s Dual version of the popular DM74LS93 s DM74LS393 dual 4-bit binary counter with individual clocks s Direct clear for each 4-bit counter s Dual 4-bit versions can significantly improve system densities by reducing counter package count by 50% s Typical maximum count frequency 35 MHz s Buffered outputs reduce possibility of collector commutation
Ordering Code:
Order Number DM74LS393M DM74LS373N Package Number M14A N14A Package Description 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150 Narrow 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter "X" to the ordering code.
Connection Diagram
Function Table
Counter Sequence (Each Counter) Count 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
H = HIGH Logic Level L = LOW Logic Level
Outputs QD L L L L L L L L H H H H H H H H QC L L L L H H H H L L L L H H H H QB L L H H L L H H L L H H L L H H QA L H L H L H L H L H L H L H L H
(c) 2000 Fairchild Semiconductor Corporation
DS006434
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DM74LS393
Logic Diagram
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DM74LS393
Absolute Maximum Ratings(Note 1)
Supply Voltage Input Voltage Clear A Operating Free Air Temperature Range Storage Temperature Range 7V 5.5V 0C to +70C -65C to +150C 7V
Note 1: The "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The parametric values defined in the Electrical Characteristics tables are not guaranteed at the absolute maximum ratings. The "Recommended Operating Conditions" table will define the conditions for actual device operation.
Recommended Operating Conditions
Symbol VCC VIH VIL IOH IOL fCLK fCLK tW tREL TA Supply Voltage HIGH Level Input Voltage LOW Level Input Voltage HIGH Level Output Current LOW Level Output Current Clock Frequency (Note 2) Clock Frequency (Note 3) Pulse Width (Note 5) A Clear HIGH Clear Release Time (Note 4)(Note 5) Free Air Operating Temperature 0 0 20 20 25 0 70 Parameter Min 4.75 2 0.8 -0.4 8 25 20 Nom 5 Max 5.25 Units V V V mA mA MHz MHz ns ns C
Note 2: CL = 15 pF, RL = 2 k, TA = 25C and VCC = 5V. Note 3: CL = 50 pF, RL = 2 k, TA = 25C and VCC = 5V. Note 4: The symbol () indicates that the falling edge of the clear pulse is used for reference. Note 5: TA = 25C, and VCC = 5V.
Electrical Characteristics
over recommended operating free air temperature range (unless otherwise noted) Symbol VI VOH VOL Parameter Input Clamp Voltage HIGH Level Output Voltage LOW Level Output Voltage II IIH IIL IOS ICC Input Current @ Max Input Voltage HIGH Level Input Current LOW Level Input Current Short Circuit Output Current Supply Current VCC = Max (Note 7) VCC = Max (Note 8) VCC = Max, VI = 0.4V Conditions VCC = Min, II = -18 mA VCC = Min, IOH = Max VIL = Max, VIH = Min VCC = Min, IOL = Max VIL = Max, VIH = Min IOL = 4 mA, VCC = Min VCC = Max, VI = 7V VCC = Max, VI = 5.5V VCC = Max, VI = 2.7V Clear A Clear A Clear A -20 15 2.7 3.4 0.35 0.25 0.5 0.4 0.1 0.2 20 40 -0.4 -1.6 -100 26 mA A mA mA mA Min Typ (Note 6) Max -1.5 Units V V
V
Note 6: All typicals are at VCC = 5V, TA = 25C. Note 7: Not more than one output should be shorted at a time, and the duration should not exceed one second. Note 8: ICC is measured with all outputs open, both CLEAR inputs grounded following momentary connection to 4.5V, and all other inputs grounded.
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DM74LS393
Switching Characteristics
at VCC = 5V and TA = 25C RL = 2 k Symbol fMAX tPLH tPHL tPLH tPHL tPHL Parameter Maximum Clock Frequency Propagation Delay Time LOW-to-HIGH Level Output Propagation Delay Time HIGH-to-LOW Level Output Propagation Delay Time LOW-to-HIGH Level Output Propagation Delay Time HIGH-to-LOW Level Output Propagation Delay Time HIGH-to-LOW Level Output From (Input) To (Output) A to QA A to QA A to QA A to QD A to QD Clear to Any Q CL = 15 pF Min 25 20 20 60 60 39 Max CL = 50 pF Min 20 24 30 87 87 45 Max MHz ns ns ns ns ns Units
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DM74LS393
Physical Dimensions inches (millimeters) unless otherwise noted
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150 Narrow Package Number M14A
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DM74LS393 Dual 4-Bit Binary Counter
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Package Number N14A
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. www.fairchildsemi.com 6 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com


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